This invention relates to methods for designing and developing models for simulating the behavior of electronic circuits, and more particularly, to methods for designing and developing models for simulating the behavior of clock signals in electronic circuits, especially if those clock signals are generated by a phase-locked loop circuit.
Simulating the behavior of an electronic circuit requires the use of a simulator, values for the input signals of the electronic circuit (sometimes referred to as stimuli), a digital representation of the electronic circuit (e.g., a simulation model), and expected values for the output signals of the electronic circuit that the simulation model is supposed to produce in response to the stimuli. The simulation model is often organized hierarchically and instantiates other simulation models, especially if the electronic circuit instantiates intellectual property (IP) blocks which often have their own simulation models.
During simulation, the simulator first loads and pre-processes the simulation model to create a simulator-internal representation that enables the computation and tracking of signals inside the electronic circuit. The simulator then feeds the stimuli to the inputs of the simulator-internal representation and propagates them successively towards the outputs of the simulator-internal representation by computing the values of intermediate signals and finally output signals when those signals reach the outputs. The simulation is based on a simulation time scale and the simulator updates the values of signals according to an ordering of events which may occur at discrete consecutive time steps of the simulation time scale. Since the events are updated at discrete time intervals and not continuously, the simulation time scale inherently has a limited resolution. The resolution of the simulation time scale may be defined by a user. As a final step, the simulator compares the values of the computed output signals to the expected output signal values. Mismatches between actual values and expected values, often referred to as simulation mismatches, indicate unexpected behavior of the electronic circuit and need to be investigated.
Simulation model shortcomings may also cause mismatches between actual and expected values. A common problem is the modeling of clock signals which are typically defined by their frequency and duty cycle. The duty cycle is the percentage of time for each clock period that the clock signal is at a high level. In simulation, clock signals are often modeled using a constant clock period and explicitly defining rising and falling clock edges within that period. The clock period is typically defined as the inverse of the clock frequency. However, due to the limited resolution of the simulation time scale, some clock periods may carry a rounding error whereas others may not. For example, a clock signal having a frequency of 100 MHz has a clock period of 10 ns. This clock period has no rounding error if the resolution of the simulation time scale is 1 ns. However, a clock signal with a frequency of 400 MHz has a clock period of 2.5 ns and thus a rounding error for the same resolution. This leads to so called edge drifting during simulation in which deviation between the rising and falling edges of clocks with rounding errors and clocks without rounding errors increases with increasing simulation time. Increased deviation over simulation time may eventually lead to changes in the ordering of simulation events and potentially cause simulation failures.
Clock signals are often generated by phase-locked loop (PLL) circuits. A phase-locked loop (PLL) circuit is an electronic circuit with a variable frequency oscillator and a phase detector. The phase-locked loop (PLL) circuit adjusts the frequency of its oscillator based on a phase comparison between an input reference clock signal and the oscillator signal in a feedback loop. Maintaining a fixed phase relationship between the two signals guarantees that their frequencies are synchronized. The phase-locked loop (PLL) circuit may further have a plurality of post-scale counters which allow a number of output clock signals having harmonically related frequencies to be produced.
Conventional simulation models for phase-locked loop circuits have modeled the oscillator frequency by deriving the frequency of the input reference clock frequency and computing a division factor in the feedback loop. This is similar to computing the oscillator period as the inverse of its frequency with the exception that the period can be adjusted if the division factor is changed dynamically. However, this approach still suffers from the edge drifting issue due to rounding errors.